PROGRAMMABLE PHASE LOCKED LOOP BOARD
Richard Hosking VK6BRO
There are thousands of ex commercial FM transceivers in use by amateurs
on the VHF bands. Earlier sets generally used fixed crystals with
band-switching for frequency control. These fixed crystals are expensive
as they have to be custom made. More recently, some sets (eg Phillips
FM880) use PLL systems with EPROM programmable frequencies. These still
involve an EPROM programmer which may not be available for many people.
The ideal would be a system with a display and up/down settable
frequencies over the entire band of interest. With the advent of
microcontrollers with on chip EEPROM, it is possible to design a user
programmable PLL board which could be used in VHF FM systems. It could
also be used in other VHF applications (eg weather receivers, aircraft
The board consists of the Atmel AT90S1200 microcontroller, a Motorola
MC145170 PLL chip and associated circuitry. Provision is made for the
board to interface with one of the common LCD 16 by 2 line displays to
provide a frequency indication. There are connections for 2 off board
VCOs for transmit and receive if required. Up to 4 pushbutton swithes
can be connected for frequency up/down and mode control. There is an
onboard dual opamp for use in the loop filter. One opamp can be
configured as a 2nd or 3rd order integrator/loop filter and the second
can be used as a DC amplifier to set loop gain.
A circuit diagram is shown in Fig 1
Modes of operation
Up to 4 IF offsets can be entered by the user. There is a memory mode
with up to 8 memory channels. The up/down keys shift frequency by one
step in standard mode and also act to scroll channels when in memory mode.
Programming PLL parameters
If both memory and mode keys are pressed at power-on then the
microcontroller enters the PLL programming routine. This routine scrolls
through a series of parameters and prompts the user to enter these using
the up/down keys. These parameters are stored in EEPROM and are read only
during normal program operation.
The first parameter to be entered is the reference divider ratio. Assuming
a 4 MHz clock,
Reference Ratio = 4000/freq spacing(KHz)
eg for a 25 KHz freq spacing the ratio will be 160
The display indicates a 6 digit number with the cursor flashing at the
current digit. The digit can be scrolled from 0 to 9 and then 0 again
using the mode key. The memory/enter key will scroll to the next digit
and on to the next parameter to be entered. "160" should be entered as
"000160" The "legal" range for the reference divider for the MC145170
is 4 to 32768
The channel spacing should be entered in KHz to allow the program to
calculate output frequency.
eg 25 KHz should be entered as "000025"
Note that there will be practical limits imposed on the channel spacing
by the performance of the PLL. In practice it is difficult to get
acceptable reference suppression if the channel spacing is less than
about 5 KHz. As the clock is 4 MHz and the min reference divider ratio
is 4 then then the maximum channel spacing is 1000 KHz.
Main Divider Limits
The user is prompted for the maximum and minimum ratios for the main
eg for a 50-54 MHz VCO with 25 KHz channel spacing the max and min ratios
54000/25 = 2160 ("002160") and
50000/25 = 2000
"Legal' main divider limits are 40 to 65535.
When the controller reaches the upper or lower limit, then further
up/down key entries have no effect.
IF offset 1 to 4
There is provision for a second VCO to be controlled from the board
This might be used for a receiver local oscillator in a transceiver
There will probably be an IF offset in this case. Assume that the IF
is 10.7 MHz and the LO is above the frequency of operation. Channel
spacing is to be 25 KHz.
Offset is therefore 10700/25 = 428
When the second VCO is selected in normal operation, the program adds
the offset to the main divider ratio . This is a 16 bit binary unsigned
addition. If a negative offset is required then the required offset
should be subtracted from 65536 eg for a 10.7 MHz negative offset:
Offset = 65536 - (10700/25)
If other than simplex operation is required then the offset is adjusted
eg for typical amateur repeater operation, the receive frequency is 600
KHz above the transmit frequency. To calculate the offset in this case
assume a 10.7 MHz IF, LO above transmit frequency, 25 KHz channel spacing
and 600 KHz repeater spacing.
Offset is (10700+600)/25 = 452
The user may enter 4 offsets
This figure is the PLL ratio for the initial frequency on powerup. The
user should enter his most used frequency. Note that offset number 1
will be associated with this startup frequency.
After all the parameters are entered and stored in EEPROM, the program
proceeds to normal operation.
Loop filter design
The board allows flexible loop filter design. There are two opamps in a
single package. The first is a differential integrator using the
differential phase detector outputs from the MC145170. If the user wants
a third order loop filter, an additional RC pole can be used at the input
to the opamp. For a second order system, this RC section can be bypassed.
The second opamp is configured as a DC amplifier to allow gain setting
and a higher VCO control voltage if desired.
There are several programs available for analysis of the loop filter
See PLL design page
for a process to allow loop filter analysis
For the purposes of analysis programs:
Phase detector gain Kp is
for the MC145170 differential outputs.
For those who are interested the source code for the PLL is available at
Source code for the Programmable PLL board
Include file for the Programmable PLL board
I would be interested in any suggestions as to improvements to the code.
This article will be updated and the board layout etc posted soon